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Intelligent Copyright Protection for Images




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ISBN 9780429243431
Published April 16, 2019 by Chapman & Hall
172 Pages 46 B/W Illustrations

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Book Description

This book describes the need of copyright protection for multimedia objects and develops an invisible image watermarking scheme to serve the purpose of copyright protection. Here intelligent systems are introduced to generate a better visual transparency with increased payload.

Table of Contents

Contents

Preface, xi

Acknowledgments, xv

About the Authors, xvii

Chapter 1 ▪ Introduction 1

1.1 INFORMATION HIDING AND COPYRIGHT

PROTECTION 1

1.1.1 Overview 1

1.1.2 Hiding Techniques 2

1.1.2.1 The Ancient Age 3

1.1.2.2 The Modern Age 6

1.2 DIGITAL WATERMARKING AS A COPYRIGHT

PROTECTION TOOL 11

1.2.1 Overview 11

1.2.2 Basic Operations 13

1.2.3 Classification 16

1.2.4 Properties for a Good Digital

Watermarking Scheme 19

1.2.5 Application 21

1.2.6 Attacks 24

Chapter 2 ▪ Perspectives on Digital Image

Watermarking 27

2.1 INTRODUCTION TO DIGITAL IMAGE 27

2.2 VARIOUS TECHNIQUES OF DIGITAL IMAGE

WATERMARKING 32

2.2.1 Spatial Domain Practices 32

2.2.2 Frequency Domain Practices 35

2.3 SOME EXISTING FRAMEWORKS FOR

DIGITAL IMAGE WATERMARKING 44

Chapter 3 ▪ Intelligent Systems Used in Copyright

Protection 59

3.1 VISUAL SALIENCY AND ITS PURPOSE IN

DIGITAL WATERMARKING 61

3.1.1 Saliency and Salient Object 61

3.1.2 The Purpose of Saliency in Digital

Watermarking 61

3.1.3 Saliency Detection and a Saliency Map 62

3.1.4 Various Saliency Map Algorithms for

Images 64

3.2 INTELLIGENT IMAGE CLUSTERING: THE

K-MEANS ALGORITHM 67

3.2.1 Data Clustering 67

3.2.2 Need for Data Clustering in Digital Image

Watermarking 70

3.2.3 K-means Algorithm for Data Clustering 71

Chapter 4 ▪ Copyright Protection Framework 75

4.1 WATERMARK EMBEDDING SYSTEM 75

Step 1: Evaluating the Saliency Map from the

Cover Image 77

Step 2: Constructing the Hiding Capacity Map

from the Saliency Map 80

Step 3: Constituting the Watermarked Image

through Adaptive LSB Replacement 83

4.2 WATERMARK EXTRACTING SYSTEM 86

Chapter 5 ▪ Hardware Implementation 91

5.1 OVERVIEW OF HARDWARE REALIZATION

FOR DIGITAL WATERMARKING 92

5.2 HARDWARE ARCHITECTURE FOR THE

PROPOSED IMAGE WATERMARKING SCHEME 96

5.2.1 Watermark Embedding System 96

5.2.2 Watermark Extracting System 100

Chapter 6 ▪ System Evaluation 105

6.1 EMBEDDING SYSTEM OUTCOMES 105

6.2 ESTIMATION OF DATA HIDING CAPACITY 108

6.3 ANALYSIS OF IMPERCEPTIBILITY OR DATA

TRANSPARENCY 109

6.3.1 Description of Image Quality Metrics,

Involved in Imperceptibility Analysis 109

6.3.2 Evaluation of Imperceptibility for the

Proposed Watermarking Scheme 115

6.4 OUTPUTS OF THE WATERMARK

EXTRACTING SYSTEM AND ITS EFFICACY IN

TERMS OF ROBUSTNESS 122

6.5 COMPARATIVE STUDY ON THE

PROFICIENCY OF THE PROPOSED

WATERMARKING SYSTEM 125

6.6 AN EVALUATION OF HARDWARE SYSTEMS

FOR THE PROPOSED WATERMARKING LOGIC 126

Chapter 7 ▪ Conclusion 131

REFERENCES 135

INDEX 151

...
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Author(s)

Biography

Mr. Subhrajit Sinha Roy received his B. Tech. in Electronics and Communication Engineering from West Bengal University of Technology in 2012 and M. Tech. in Telecommunication from RCC Institute of Information Technology (under West Bengal University of Technology), Kolkata, India, in 2015. At present he is an Assistant Professor in the department of Electronics and Communication Engineering at Global Institute of Management and Technology, Krishnagar, West Bengal, India. He has also been enrolled in the Department of Radio Physics and Electronics under Calcutta University for Ph.D in Engineering and Technology. Till date he has six research publications in international journals, conference proceedings and edited volumes to his credit. His field of interest spans digital image processing, information hiding, FPGA based system design, low power VLSI design and quantum computing.

Dr. Abhishek Basu received his B. Tech. in Electronics and Telecommunication Engineering from West Bengal University of Technology in the year 2005, M. Tech. in VLSI Design from Institute of Radio Physics and Electronics, University of Calcutta, India in 2008 and Ph. D (Engg) from Jadavpur University, India in 2015. He is currently the Assistant Professor and Head of the Department of Electronics and Communication Engineering department of RCC Institute of Information Technology, Kolkata, India. He served as under graduate Program coordinator in the above mentioned Dept. during 30th march 2016 to 1st January, 2017. He is co-editor of a book and has more than 40 research publications in international journals, conference proceedings and edited volumes to his credit. He is the hospitality chair of International Conference on Intelligent Control, Power and Instrumentation (ICICPI 2016), during October 21th -23th, 2016. He is the member of the organizing and technical program committees of several national and international conferences. His research interests include digital image processing, visual information hiding, IP protection technique, FPGA based system design, low power VLSI Design and embedded system design. Dr. Basu is a life member of Indian Association for Productivity, Quality and Reliability, India.

Dr. Avik Chattopadhyay received his B. Tech. in Electronics and Telecommunication Engineering from West Bengal University of Technology in the year 2006, M. Tech. (in VLSI Design) and Ph. D. (Tech.) from the Institute of Radio Physics and Electronics, University of Calcutta, India in 2009 and 2013, respectively. He is currently an Assistant Professor with the Institute of Radio Physics and Electronics, University of Calcutta, Kolkata, India. Prior to this, he served as Assistant Professor of Electrical and Electronics Engineering department of Birla Institute of Technology and Science, Pilani, Rajasthan, India almost for two years. He is co-author of a book-chapter and has more than 20 research publications in international journals, and conference proceedings to his credit. His research interests include design and analysis of novel structures of MOSFETs, study of post-CMOS devices for low power VLSI applications, and designing of FPGA based system.